1. Field of the Invention
This invention relates to semiconductor products and more particularly to memory arrays utilizing sense amplifier circuits.
2. Description of the Related Art
Large memory arrays are used for storage of data and program values in conventional computer systems. In order to increase the amount of data that can be stored in memories, the memory cell which stores the digital value is typically made as small as practical. Bit lines are used to convey the information stored in the storage cells when the memory array is read. However, the voltage differences between a one and a zero, typically represented as a differential voltage on the bit lines is relatively small due to the desire to keep the size of the memory cell small. Therefore, sense amplifier circuits are used to sense whether the stored value represents a digital zero or a one and to amplify the signal to a voltage value which can be used by other circuitry utilizing the stored data and program values.
In addition to functioning as a sense amplifier, some designs have exploited the sense amplifiers for testing purposes to provide greater test visibility into the memory array than available with other test techniques. Particularly, one test approach provides for scan access to the sense amplifiers used in the memory array. Such an approach arranges the sense amplifiers into a scan chain so that the values in the sense amplifiers can be serially shifted (or scanned) through the scan chain until the shifted values are made available to an external observer. However, scanning typically requires a two flip-flop or latch configuration for each data bit desired to be shifted out.
Thus, designs such as the one shown in FIG. 1, showing several sense amplifiers configured in a scan chain, have been utilized for scanning sense amplifiers. Once data has been read from the storage array into sense amplifiers 101, 102 and 103, the data may be shifted into slave flip-flops 104, 105 and 106 on assertion of clock 107. The data may then be shifted through the scan chain by alternately applying clock 110 to shift data into the master flip-flops from the slave flip-flops and clock 107 to shift data into the slave flip-flops. The sequence of alternate clocks is applied until data has been shifted completely through the scan chain.
The approach shown in FIG. 1 requires an extra (or shadow) flip-flop for each sense amplifier. That approach is costly because the extra flip-flop occupies an area in each column of the array which can be comparable to the size of the sense amplifier itself. Further, the inclusion of the slave flip-flop can slow down the normal operation of the sense amplifier because of the increased wiring required to connect to the slave flip-flop to the sense amplifiers.
In order to eliminate the need for the slave sense amplifiers, another prior art sense amplifier scan approach configures alternate sense amplifier latches as master and slave latches such that alternate sense amplifier latches are allowed to overwrite data stored in a next adjacent latch. However, such prior art techniques have not considered efficient design of such master/slave latches. Thus, there is a need to provide a scan approach for sense amplifiers that addresses the issue of circuit minimization and efficiency in addition to the desire to avoid costly extra logic.